//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 			Arizona State University
// Engineer: 			Joe Boeding
// 						Taylor Wood
//
// Create Date:    	14:44:55 03/01/2013 
// Design Name: 		NOR
// Module Name:    	nor_cmos 
// Project Name: 		LAB #1
// Target Devices: 	Xilinx Spartan6 XC6LX16-CS324
// Tool versions: 	Xilinx ISE 14.2
// Description: 		
//		Using "pmos" and "nmos" Verilog switch-level primitives 
//		create a module named "NOR" gate
//
// Dependencies: 		NONE
//
// Revision: 		
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module PED(   //Port Declarations
    input sig,   // Signal input to be monitored
    input clk,      // Synchronous Clock Input
    input reset_b,    // An active low input which resets the logic to a default state
    output pulse    // A single clock wide pulse to indicate that a Positive edge has
    );           // has been detected
//------------Signal Declarations/Internal Variables-------- 
reg temp_reg_i;       // One clock shifted signal
wire d1_inv_signal_i; // One clock shifted and inverted signal
//-------------Code Starts Here--------- 
always @ (posedge clk or negedge reset_b) begin
if (reset_b == 1'b0) 
  temp_reg_i <= 1'b0;  
else 
  temp_reg_i <= sig; 
end 
assign d1_inv_signal_i = !temp_reg_i; 
assign pulse = sig & d1_inv_signal_i; 
endmodule